I am trying to run my testbench to do a simulation check after Xilinx has done place and route for the design. When it brings modelsim up and tries to simulate it gives errors such as:
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
Can anyone tell me what this error means or what option I need to set in ISE 5.2 to fix this?
yes, but it seems to hang and not stop when i run the compxlib
also, since xilinx ise 5.1 generates a new .v file for every step does that mean I have to create a new testbench for the new *.v file that ise generated for the post layout simulation?
have u added the testbench in your project?? if you added ur testbench, it should not having this problem.. if it still having this problem, look into ur xilinx ISE folder and find simulation library