Simulating VHDL AMS model in cadence.

[BMR]

Dear all,

I have a VHDL-AMS model and I need to simulate it. As in verilog A/AMS once the code is complied a symbol is created .I expected the same for VHDL-AMS ,but nothing happened.
Any help would be appreciated .For your reference I have pasted the code below.
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library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
entity \digRfPllTdcDecoder\ is
generic (

TD_Q : time := 0 ps;
SEED : integer := -1;
SELQ : integer := 4;
DTDC : integer := 48;
WTDC : integer := 6
);

port (
Q: in std_logic_vector (DTDC downto 1);
clk : in std_logic;
tdc_rise : out unsigned (WTDC-1 downto 0);
tdc_skip : out std_logic;
BC : out unsigned (WTDC-1 downto 0)
);

architecture rtl of pf_dec is
signal q1: std_logic_vector (DTDC downto 1);
constant SLV_0: std_logic_vector (SELQ downto 1):= (others=>'0');
begin

process (Q)
variable s1: integer := SEED;
variable initial: boolean := true;
variable randvar: natural;
variable q: std_logic_vector (DTDC downto 1);

begin
for k in 1 to DTDC loop

if Q(k)='X' then
sub_randb(randvar);
if randvar = 0 then q(k) :='0';
elsif randvar=1 then q(k) := '1';
end if;
else
q(k) := Q(k);
end if;
end loop;

q1 <= q;
end if;
end process;


process (clk, q1)
variable rise: integer range DTDC-1 downto 0;
variable fall: integer range DTDC-1 downto 0;
variable half_period: integer range DTDC-1 downto 0;
variable skip: std_logic;
begin
if clk='1' then
rise := 0;
for k in 2 to DTDC loop
if q1(k-1)='1' and q1(k)='0'then
rise := k-1;
exit;
end if;
end loop;


fall := 0;
for k in 2 to DTDC loop
if q1(k-1)='0' and q1(k)='1' then
fall := k-1;
exit;
end if;
end loop;

tdc_rise <= to_unsigned(rise, WTDC)

after TD_Q ;

if q1(SELQ downto 1) = SLV_0 then
skip := '1';
else
skip := '0';
end if;

tdc_skip <= skip

after TD_Q ;

if rise > fall then
half_period := rise - fall;
else
half_period := fall - rise;
end if;

BC <= to_unsigned(half_period, WTDC)

after TD_Q ;
end if;
end process;
end \digRfPllTdcDecoder\;


BR,
BMR