At the output, looking into each output you will see C2 in parallel with the effective capacitance seen looking backwards into the feedback cap C1. If you define a feedback factor b=C1/(C1+C1+Cin), where Cin is the input cap of the OTA to ground, then looking back into C1 you will see Ceff=(1-b)C1. Then your load cap for each output is C2+Ceff.
When it comes to slew rate, you should give a large voltage step at the input of the circuit. Since step edge is very sharp, the OTA will not be able to respond to that and then at the input of the OTA you'll see instantaneously a corresponding step defined just by the capacitive divider, as if the OTA was not even there. If the OTA input step is bigger than about sgrt(2)Vov of the input diff pair, then the OTA will slew. So, just give a large enough step to make it slew and look at the results.
What do you mean by result being degraded? I assume you see the initial transient. You should probably simulate for much longer than 17.5us because 100MOhm with 0.5pF results in timeconstant of 50us. When you put 1kOhm resistor, then the capacitor is practically shunted and you have an integrator - 1k resistor and the feedback capacitor. The UGBW of the integrator is something like 320MHz, which means that the gain at 1MHz is 50dB. That's the reason why I suggested 100MOhm resistor. Actually, you can set initial conditions of 1.65V for the two OTA inputs and this will most probably speed up the transient.
Why reverse?AV(closed)=C1(input)/C1(feedback) which is reverse to the theoritical low ??
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