I generated a netlist using design Compiler and now I would like to test it in Modelsim by means of a TB. However, when I am running the netlist, the tool can not find the gates (AND, OR, FFs, etc), how can I specify them in order to see the waveforms in modelsim?
on the vsim command line add the simulation libraries with the -L <library_name> option.
If you don't already have a compiled simulation library then you'll need to compile the vendors simulation library code into the library using vlog (if library is in Verilog).