simulating long strings in VHDL

[shaiko]

Hello people,

I designed an FPGA UART block that respondes to various user inputs via a console connection.

For example:
If the user types "day of week" the FPGA respondes "sunday"...

In order to verify the design I simulate the commands by bit inputs to the Rx channel...if every ASCII char is 8 bits so a 10 character message will involes sending 80 bits.

I do it using the testbench "after" keyword - for example:
'1' after 2us, '0' after 7us, '1' after 8us...etc

This is very time consuming for long words. Is there a simpler way to do it?

 

[TrickyDicky]

yes.
What you want to build is a bus functional model (BFM). this is just behavioural code that behavious like the bus you're simulating.

for example

procedure send_string(        str     : in  string;
                       signal clk     : in  std_logic;
                       signal op      : out std_logic
                      ) is  
  
  variable temp_ascii   : unsigned(7 downto 0);
begin
  
  for i in str'range loop
    
    temp_ascii := to_unsigned( character'pos( str(i) ), 8 );  --character type is positioned according to ascii codes
    
    for j in temp_ascii'range loop
      op <= temp_ascii(j);
      
      wait until rising_edge(clk);      
    end loop;
  end loop;
  
end procedure;

.....................

process
begin
  send_string( str => "This is a very long string but it will transmit each character bit by bit",
               clk => clk,
               op  => op
             );
  wait;
end process;

 

[shaiko]

Thanks!!!

Of course this kind of code isn't synthesizable and it's only for simulation purposes - Do "procedures" have any uses in synthesis?

 

[TrickyDicky]

yes, you can use procedures in synthesisable code. But obviously not this one.

But I cant think of a synthesis situation where Ive found a procedure really tidies things up or helps me much. I use them a lot in testbenches though.