simulating cic ipcore

dipin · Feb 2, 2017

hi,

i just designed a cic filter and got out put. now i need to cross check the output with ip core output in quartus 16.0 lite edition.

but when i try to simulate the generated ip core using a test bench...its showing error..

Error (10149): Verilog HDL Declaration error at alt_cic_core.sv(37): identifier "line_length" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at alt_cic_core.sv(37): identifier "bytes" is already declared in the present scope
Error (10170): Verilog HDL syntax error at alt_cic_core.sv(37) near text: ")"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at http://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

the alt_cic_core is a quartus generated file.. so is it possible to simulate an ip core???

when i checked online..they are saying that ""its not possible to simulate hdl files in ip core..they are synthesize only...""
is it possible ,,can anybody tell me what iam missing
in xilinx its possible..because i done it before .....

thanks and regards

FvM · Feb 2, 2017

alt_cic_core.sv is an encrypted file used for synthesis only and can be simulated. The simulation need to use the dedicated simulation model generated along with the synthesizable core.

dipin · Feb 3, 2017

FvM said:
alt_cic_core.sv is an encrypted file used for synthesis only and can be simulated. The simulation need to use the dedicated simulation model generated along with the synthesizable core.

thanks for the replay fvm,

i ticked the generate simulation model during the ip generation....then there is a folder called simulation. but both the files are same.. i mean files in synthesize & simulation folder are same. can you please give some more information about this ....thanks very much in advance.
i just simulated the files in simulation folder which is throwing same error

regards

simulating cic ipcore

dipin

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FvM

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dipin

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simulating cic ipcore

dipin

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