Simulating bitstream/analog output?

[davorin]

Which VHDL/Verilog Simulator can use external file for bitstream input and simulate analog output?

Like: feeding mpeg stream and writing to wave file?

 

[radix]

What do you mean by "simulating an analog output"? What is driving the analog output? Is there an analog/digital interface?

Radix

 

[davorin]

Let's say if the FPGA is used to drive a DAC with PCM stream...

So I could capture the PCM stream to a file for verification...to see if it really generates a .pcm file suitable for standard PCM DAC's

 

[radix]

davorin,

It sounds like what you're trying to do is simple file i/o and that is supported directly by the verilog and vhdl languages. You just need to setup a testbench that reads the input file and applies it to a top-level pin of your design. To capture the data you're interested in your testbench would just read that top-level pin and dump it to a file. You can either test the output data in the testbench during simulation or use a script to parse the file post simulation.

Radix

 

[venkatesankalidass]

It sounds like what you're trying to do is simple file i/o and that is supported directly by the verilog and vhdl languages. You just need to setup a testbench that reads the input file and applies it to a top-level pin of your design. To capture the data you're interested in your testbench would just read that top-level pin and dump it to a file. You can either test the output data in the testbench during simulation or use a script to parse the file post simulation

 

[kumardev]

Can someone help me debug this while loop...

module bitrev(clk);
input clk;
reg[8:0] in_r[0:8];
reg[8:0] out_r[0:8];
reg[8:0] tmp_r;
integer i;
integer j=0;
integer n1=4; // for N-point n1 = 8/2
integer n2=4;

initial begin
for (i=0; i < 8; i= i+1)
begin
n1 = n2;
while ( j >= n1 )
begin
j = j - n1;
n1 = n1/2;
end
j = j + n1;

if (i < j)
begin
tmp_r = in_r;
in_r = in_r[j];
in_r[j] = tmp_r;
tmp_r = out_r;
out_r = out_r[j];
out_r[j] = tmp_r;
end
end
end

endmodule