Simulating 6 sigma CMOS device variations in Cadence Spectre

Status
Not open for further replies.
A

analogTechie

Junior Member level 1
Joined
Nov 2, 2004
Messages
15
Helped
3
Reputation
6
Reaction score
0
Trophy points
1,281
Location
USA
Activity points
170
Hi all,

Could anyone comment (or share references) on simulating device variations in Cadence Spectre, particularly using the "VTA adder" methodology ? Thanks ~!
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…