Why do you simulate switches?
What performance parameters do you want to get through this simulation?
Generally speak,Charge injection effect must be considered carefully for high performance S/H circuit.
Regards,
wael_wael said:
hi every body
could some one suggest how i can simulate the switches for S&H?
best regards:?:
Yes, you are right, Jerry.
On-resistance and switch bandwidth are important parameter for S/H.
If wael_wael know his target, then he resolve half of his problem
I think there are standard means to simulate these performance Jerryzhao mentioned above. Is it right?
Regards,
jerryzhao said:
1 simulation the switch's on resistance.
2 simulation the switch's bandwidth.
3 calculate the clock feedthrough effect.
How to simulate?
First you must know how to calculate. you can reference some book, such as CMOS Analog Circuit Design P.E.Allen.
The simulation is easy. only do ac simulation. and switch's DC scan. the R=V/I.
Added after 2 minutes:
For the whole S/H you should do .tran simulation to check the accuracy.
I faced the same problem for my Switched Capacitor ADC some years before. The problem was that when the switch was off there was a division with zero that was not allowing simulation to run. The best workaround I found was to simulate the switch with a voltage generator or a voltage controled switch ( I think CADENCE has a device like this) . The whole idea, is to control with voltage the passing or not of the voltage signal from a point. It is the only simulation that was near to reality, although you won't be able to introduce all the effects of a real MOS switch.
"when the switch was off there was a division with zero that was not allowing simulation to run. "
Sorry, I am not face such issue. I use Hspice to do similation. Maybe you should check your simulation file's setup,(shuch as, input signal, DC path etc.) I hope I do not confuse you.
When simulation g a model you start from the ideal operation. For a switch is to instantenusly transfer the voltage or the current on the other side of the switch.
Then you know that you are going to use MOS switches. These have a specific Ohmic resistance, paracitic capacitance and clock feedthrough issues that you have to implement to your model one by one to check what is the value of its one that you can allow to exist and what is causing big troubles with your deign and you have to negate. I.E. you will have free carriers running arbitary when the MOS switch is closed. If you are dealing with a S/H circuit this usually is not desired. So you put dummies on both side of the MOS switch to equally spread these carriers and not to feed them all to the S/H capacitance. If you don't model it, you can't see if it creates a problem and where this problem comes from.