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$simprobe Verilog - ams

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Fabien

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Dear all!

I've a some difficulties to modelized analog blocks: for the design of an ADC, there are two blocks who interact with each other.

I'm trying to use the $simprobe command to pick-up a varname from the other blocks like this:


model_1
real probe;
probe= $simprobe("model_2","varname");

model_2
real varname = 1.12;

Question: why the real probe won't pick-up the value of varname?
Any idea how to do this?

Thank you very much for your help!!!
 

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