[SOLVED] Simple VHDL code but not synthesizable(newb)

[3wais]

I want the output to be high for one clock cycle after a high edge of an input signal is detected
so I tried this code
but it can not be synthesized

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Counter is
    Port ( Start : in STD_LOGIC;
			  CLK : in  STD_LOGIC;
           Count : out  STD_LOGIC);
end Counter;

architecture Behavioral of Counter is
begin
process (CLK,Start)
begin
if (Start'event and Start = '1') then
Count <= '1';
elsif (CLK'event and CLK = '1') then
Count <= '0';
end if;
end process;
end Behavioral;

 

[barry]

You can't have two 'event statements in one process (that implies two clocks)

Try this (assumes START is synchronous with clk):

---

Code VHDL - [expand]
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process(clk)
variable start_dly:std_logic;
begin
if clk='1' and clk'event then
       if start='1' and start_dly='0' then
            count<='1';
      else
            count<='0'';
     end if;
    start_dly:=start;
end if;
end process;

---

 

[FvM]

A toggle synchronizer is the usual safe solution without requiring any assumptions about timing relation of both signals.

process(start)
begin
  if rising_edge(start)
    toggle <= NOT toggle;
  end if;
end process;
process(clk)
begin
  if rising_edge(clk)
    sync_chain(2 downto 0) <= sync_chain(1 downto 0) & toggle;
    count <= sync_chain(2) XOR sync_chain(1);  
  end if;
end process;
end;

 

[std_match]

If you know that the start pulse length is longer than a clock cycle, you can simplify FvM's code like this:

---

Code VHDL - [expand]
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process(clk)
begin
  if rising_edge(clk)
    sync_chain(2 downto 0) <= sync_chain(1 downto 0) & start;
    count <= not sync_chain(2) AND sync_chain(1);  
  end if;
end process;

---

 

[mikeyates]

Hi. You need to think hardware, don't program in VHDL like you are software engineer. In fact all you need is produce a D-Type flip flop. This is not a counter!!

library ieee;
use ieee.std_logic_1164.all;

entity Counter is
port (
CLK : in std_logic; -- clock use to drive FF
START : in std_logic; -- D in od FF
COUNT : out std_logic -- Q out of D type FF
);

architecture rtl of counter is
begin
-- make a d type flop
d_ff: process(CLK)
begin
if rising_edge(CLK) then
COUNT <= START;
end if;

end process d_ff;

end rtl;

---------- Post added at 09:29 ---------- Previous post was at 09:20 ----------

should also mention, you can only have one clock per process, e.g. only one 'even per process, also my solution implies that the start signal is synchronous with the clk signal

 

[FvM]

This is not a counter!!

I think 3wais knows that his design isn't a counter. It's rather intended as input preprocessing for a counter, I guess.

In fact all you need is produce a D-Type flip flop.

The original post doesn't exactly describe the properties of the input signal, particularly it's duration and relation to the clock. But it would be too optimistic to assume a fixed timing relation. Otherwise a synchronizer, either the synchronous edge detector suggested by std_match or the toggle synchronizer will be needed to detect each input event reliably.

The simple D flip-flop will miss the described functionality "output to be high for one clock cycle after a high edge of an input signal is detected" in these cases:
- detect pulses shorter than a clock cycle only by chance
- generate a too long output pulse in other cases
- show unpredictable behaviour when the input edge falls inside the setup and hold window of the D flip-flop

 

[juansiahaan]

You can't have two 'event statements in one process (that implies two clocks)

Try this (assumes START is synchronous with clk):

---

Code VHDL - [expand]
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process(clk)
variable start_dly:std_logic;
begin
if clk='1' and clk'event then
       if start='1' and start_dly='0' then
            count<='1';
      else
            count<='0'';
     end if;
    start_dly:=start;
end if;
end process;

---

 if start='1' and start_dly='0' then

Could you explain what is the meaning of that line? I've seen codes using that lines...and what is the difference when it is

if start = '0' and start_dly = '1' then

??

Thanks and regards..

Juan

 

[barry]

The statement "if start='1' and start_dly='0' then" will be true after a rising edge. The statement "if start = '0' and start_dly = '1' then" will be true after a falling edge. Drawing a timing diagram will help you understand this.