Simple verilog question

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ankit12345

Banned
always@(posedg clk)

begin

a<=1;
a<=0;
end

whats the value of a?????

sheik_vb

Member level 3
This will report Simulation Error!!!!!!!!!!!!.

aji_vlsi

sheik_vb said:
This will report Simulation Error!!!!!!!!!!!!.

Why do you say that? It shouldn't - unless I missed something obvious

Ajeetha, CVC
www.noveldv.com

ankit12345 said:
always@(posedg clk)

begin

a<=1;
a<=0;
end

whats the value of a?????

Ankit,
Sounds like an interview question? Why not simulate it and see it for yourself?

Regards
Ajeetha, CVC
www.noveldv.com

shiv_emf

a=x
as both statements get executed in last simulation time ..
always@(posedge clk)
a<=1;

always@(posedge clk)
a<=0;

this will also result in a=x

hyy95120

Member level 1
you should compile this code to logic gates and see what will the result look like.

Simulator is not the final gates.

ankit12345

Banned
Dear Ajeetha,

ur right.........its interview question........

Any one tried this????????

vinod_g

Member level 4
I think it depends on the simulator, whichever the statement executed last will have that value................................

nand_gates

Code:
always@(posedge clk)
a<=1;

always@(posedge clk)
a<=0;

This will make a=x;

Code:
always@(posedge clk)

begin

a<=1;
a<=0;
end
In this case a = 0 last driven value!
No need to do sims its a common sense!

ankit12345

Banned
Wellllllllllllllllllllllllllll......................

my system got hanged when i ran this code......in windows and linux too.............

any one tried???????

nand_gates

POST ur code here so that we can try it on our end!

subramanyam

Member level 3
Code:
always@(posedge clk)
begin
a<=1;
a<=0;
end

In this case a = 0 is the answer and is obvious as is the last executed statement.

Code:
always@(posedge clk)
a<=1;

always@(posedge clk)
a<=0;

when simulated on modelsim the answer is '0'. can anyone run it on other simulators and plz post the answer for this second code.

How the simulator will run the second case ?? and how the answer is different on deifferent simulators ??

vlsi_whiz

Full Member level 4
The answer to this question depends on the simulator... For the first code where the two assignments are done in the same always block the process is as follows:

1. When the code is compiled and simulated, the simulator assigns 1 temporary register for the signal 'a'.
2. During the first tick/time event, the signal 'a' gets the value '1'.
3. In the next tick, the same signal is assigned '0'.
4. Since there are no more assignments after this, the final value is the last assigned value, ie, '0'.

zhangpengyu

Full Member level 3
a=0
see IEEE standard

deh_fuhrer

Full Member level 5
simulator dependent..a might get the value 0 or may be 1..

nmurthy

Member level 1
Here a will get the value of 0

As we all know in race between two or more NBA ,last NBA wins
for the case mentioned
a<=1;
a<=0;

hope it helped you

cnspy

Full Member level 3
How can you write this kind of code?

vinod488

Junior Member level 3
hi,

I Think a<=0 comes out.
Sometimes it depends on simulator which ur using.

Regards,
Vinod

verilog_always

Member level 2
Code:
always@(posedge clk)
a<=1;

always@(posedge clk)
a<=0;

Can't we get multiple driver problem here?

omara007

No .. it doesn't depend on the simulator .. you sometimes feel that it's simulator dependant because sometimes each simulator has some defaults, but still u can change them ..

The original code will definetly result in : a = 0, regardless of the simulator ... simply because the statements inside the process are sequential .. while outside the process, they are concurrent .. in other words, the signal gets the value of the last assignment, which is '0' in this case ..

On the other hand, you can't assign values to the same signal in 2 different processes .. this is prohibted in RTL .. unless you release the control of the signal from one process to the other .. which is also not adviced, but some designers do it ..

satya_422

Member level 3
the result would be a=x because the blocking statements execute concurrently so the both statemts execute simultanoeusly if im not clear please help me

nand_gates said:
Code:
always@(posedge clk)
a<=1;

always@(posedge clk)
a<=0;

This will make a=x;

Code:
always@(posedge clk)

begin

a<=1;
a<=0;
end
In this case a = 0 last driven value!
No need to do sims its a common sense!

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