Hi all, I think this is a fairly trivial question for those experienced in verilog design, but I haven't been able to find any explicit answers
I'm writing a module where I am calculating frequency of an incoming signal, by first counting the number of clock cycles between change state of incoming signals. The number of clock cycles is stored in a 32 bit register "count [31:0]". To find find frequency, I use the function "frequency =6E-1/(20e-9 * count)" however when I try to compile this in quartus, I get "real numbers are not supported" and "real variable data types not supported". I can put 6E-1/20e-9 into a register, and divide a register by a register which can be compiled, but uses a huge amount of CPLD resources after quartus automatically infers a divider from the megafunction library.
So my question is how can I divide a real number by the number stored in the register using verilog?