adgjl40112
Newbie level 5
Simple verilog question.
Hey guys, I just get a little confused about if it is acceptable to write verilog code like
BTW, are nested loops synthesizable?
Hey guys, I just get a little confused about if it is acceptable to write verilog code like
Code:
reg [3:0] z;
always@(z)
begin
if (z == 4'd3)
z = 4'd0;
else
z = z;
end
BTW, are nested loops synthesizable?