Simple verilog question. - are nested loops synthesizable?

adgjl40112 · Mar 28, 2010

Simple verilog question.

Hey guys, I just get a little confused about if it is acceptable to write verilog code like

Code:

reg [3:0] z;

always@(z)
begin
   if (z == 4'd3)
      z = 4'd0;
   else
      z = z;
end

BTW, are nested loops synthesizable?

RBB · Mar 28, 2010

Simple verilog question.

That is acceptable, although i would synthesize into a latch.
For loops are synthesizable.

adgjl40112 · Mar 29, 2010

Re: Simple verilog question.

Thx for ur reply.
Still have another question. Is it abnormal that I intend to use latch in the circuit? I am really lack of hardware component.

ANother thing is I use a multidimensional memory to store something.
For eg.
reg[5:0] a[0:5][0:5];
I just want if array any index j of a[1][j] != 5'b00000, then output 1;
else output zero.

How can I achieve this?

Simple verilog question. - are nested loops synthesizable?

adgjl40112

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RBB

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adgjl40112

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Simple verilog question. - are nested loops synthesizable?

adgjl40112

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RBB

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