Simple Verilog code and output

[spritbille]

Hey. With the verilog code below, then a while after reset_mf_b has been released sum will become a cyclical sequence. What is this repeated output sequence of sum?

always @(posedge clk_mf or negedge reset_mf_b)

    if(!reset_mf_b)

    begin

      a_tmp <= 5;

      sum   <= 0;

    end

    else

    begin

      a_tmp <= a_tmp +1;

      sum   <= a_tmp +2;

      if(sum >= 12)

        a_tmp <= 5;

    end

---------- Post added at 09:39 ---------- Previous post was at 09:37 ----------

My idea is that the output sequence of sum will be: 7,8,9,10,11,12,13 (repeats) …