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simple traffic light system implementations (verilog)

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simple traffic light system implementatoin (verilog)

this is a simple traffic light implementation in verilog. something is wrong and i think it's because of timer. the output should be red->yellow->green, instead it is yellow->red->green->red->green->red->green->yellow and all over again. any help is appreciated.

design:
Code:
module traffic_lights(red,yellow,green, clk,rst);
  output reg red,yellow,green;
  input clk,rst;
  
  reg [2:0] timer;
  reg [3:0] state;
  reg [3:0] next_state;
  
  parameter RED=4'b0000;
  parameter YELLOW_1=4'b0001;
  parameter YELLOW_2=4'b0010;
  parameter GREEN=4'b0100;
  
  
  always @(posedge clk) begin
    case(state)
      RED: begin
        if(timer<3'b101) begin
          next_state<=RED;
          timer<=timer+1;
        end
        else begin
          next_state<=YELLOW_1;
          timer<=0;
        end
      end
      
      YELLOW_1: begin
        if(timer<3'b001) begin
          next_state<=YELLOW_1;
          timer<=timer+1;
        end
        else begin
          next_state<=GREEN;
          timer<=0;
        end
      end
      
      GREEN: begin
        if(timer<3'b101) begin
          next_state<=GREEN;
          timer<=timer+1;
        end
        else begin
          next_state<=YELLOW_2;
          timer<=0;
        end
      end
      
      YELLOW_2: begin
        if(timer<3'b001) begin
          next_state<=YELLOW_2;
          timer<=timer+1;
        end
        else begin
          next_state<=RED;
          timer<=0;
        end
      end
      
      default: begin state<=RED; end
    endcase
  end
    
  always @(posedge clk) begin
    if(rst==0) state<=next_state;
    else state<=RED;
  end
    
  always @(posedge clk) begin
    case(state)
      RED: 		begin red=1; yellow=0; green=0; end
      YELLOW_1: begin red=0; yellow=1; green=0; end
      YELLOW_2: begin red=0; yellow=1; green=0; end
      GREEN: 	begin red=0; yellow=0; green=1; end
      default:  begin red=1; yellow=0; green=0; end
    endcase
  end
  
endmodule
 

Re: simple traffic light system implementatoin (verilog)

Did you write a testbench and debug your code in a simulator?
 

Re: simple traffic light system implementatoin (verilog)

Why do you have both the next_state assignment and the state assignment in clocked (edge triggered) always blocks?

It looks like you are trying to implement a two always block FSM with the combinational next_state logic and the state register (synchronous portion). At a minimum change the first always to always @* begin so it is combinational. You will also have to change the timer code to have a separate synchronous always block just like the state/next_state. I avoid coding this way with embedded counters and such in a two always block FSM as you can end up with a mealy machine that you didn't expect and a much lower clock frequency in the design.

I would suggest you get rid of the next_state stuff and assign the state directly in the first always block (resulting in the one always block FSM style).

The ordering of the colors is likely due to this extra delay of the next_state getting assigned to state.
 

Re: simple traffic light system implementatoin (verilog)

i changed the first always to always @* begin and now only clk is synchronously changed, others are either x or 0 for the whole simulation time.

i need to use "next state logic" -> "current state logic" -> "output logic" logic.

and where and how should i separate timer code?

this is the testbench
Code:
module test_traffic_lights;
  wire red;
  wire yellow;
  wire green;
  
  reg clk,rst;
  reg [2:0] timer;
  reg [3:0] state;
  reg [3:0] next_state;
  
  parameter RED=4'b0000;
  parameter YELLOW_1=4'b0001;
  parameter YELLOW_2=4'b0010;
  parameter GREEN=4'b0100;
  
  traffic_lights tl(.red(red), .yellow(yellow), .green(green), .clk(clk), .rst(rst));
  
  initial begin    
    clk=0;
    rst=0;
    state=RED;
    
    #400 $finish;
    
  end
  
  always #5 clk=~clk;
endmodule
 

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