Simple synchronisng problem.

[nesta]

Hi VhdlExperts,

I have very simple doubt on synchronising data.

I have 2 logical blocks which outputs (8bit vector) for further processing at the next block-3;
The data to the block-1 might come faster than the data to the block-2 and similarly either of them might output faster, so how do i synchronise between
these two modules.

The output of blk-1 & 2 are fed as input to the blk-3. what is the best way to synchronise between 2 blocks so that
the blk-3 starts processing only after the arrival of two inputs and dont miss any of the inputs.

Blk-1---\______

Blk-2 ----------Blk-3


Thanks in advance,
Nesta

 

[lucbra]

you actually formulated the answer already...
you are passing data from one clock domain to another. This can be done with a FIFO (distributed) with read and write clock.

 

[jimmy_tag]

just set the flag for each block.

 

[FvM]

Either if you use synchronization handshake or (more complicated) FIFOs. You have to guarantee, that the average data amount sourced from block 1 is equal to the amount from block 2. The condidtion isn't mentioned in your specification.

you are passing data from one clock domain to another

Nothing has been said about multiple clock domains yet.