TSLexi
Newbie level 5
Hi guys! I'm trying to design an OTP encryption chip for a telephone. Here's the bit file:
The key pin of module will be connected to a PUF to generate a random stream. In one instance of the module, the cleartext pin will be connected to the microphone and the ciphertext pin will be connected to wherever the sound goes after leaving the mic, in another instance vice versa. Aka, it's in series with the phone I/O.
Obviously, this isn't for a real telephone, as I doubt telephone lines have a 1 bit bandwidth. It was a little project I'm doing to learn Verilog. I already know C++, and I'm trying to get into hardware design.
Does the encrypt module need a clock signal, or can it be asynchronous.
Thanks!
Code Verilog - [expand]
The key pin of module will be connected to a PUF to generate a random stream. In one instance of the module, the cleartext pin will be connected to the microphone and the ciphertext pin will be connected to wherever the sound goes after leaving the mic, in another instance vice versa. Aka, it's in series with the phone I/O.
Obviously, this isn't for a real telephone, as I doubt telephone lines have a 1 bit bandwidth. It was a little project I'm doing to learn Verilog. I already know C++, and I'm trying to get into hardware design.
Does the encrypt module need a clock signal, or can it be asynchronous.
Thanks!
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