simple FET Question- help needed

[hemant03]

FET Question

Hi,
I am using an N channel enhancement FET in my circuitry to ensure that I block positive voltages and allow negative voltages. I have tried to simulate the following circuit (attached). The Vgs(th) is 4V (for IRFL104). I am able to see an output voltage on drain eventhough the Vgs(th) is -5V (as gate is grounded). I am unable to understand the reason for that?

Thanks,
- Hemant

 

[dunn]

Re: FET Question

Check how the IRFL104 has been made up.

 

[checkmate]

Re: FET Question

Firstly, what's VGG?
Also, do remember that the FET has a body diode across drain-source in reverse.

 

[hemant03]

Re: FET Question

Hi,
Vgg is the output. Basically my intention is to see V1 = Vgg when V1 is negative and no voltage when V1 is positive. I am trying to use the Vgs(th) concept and for an enhancement mode , Vgs is anywhere around 1 to 4 V depending on the type of FET. My problem is when Vgs is negative (as Vg is 0 and Vs is 4), I am still seeing V1 = Vgg when the FET should actually be OFF.

Thanks,
- Hemant

 

[skowe26]

FET Question

Hi.

Thats because of the body diode as mentioned by Checkmate.

 

[FvM]

FET Question

Yes. Knowing how to draw simulations schematics in LTSpice is fine. Reading datasheets or text books is useful, too.

 

[dunn]

Re: FET Question

You may want to download an evaluation circuit and have a look how they have "designed" an N channel enhancement FET.