snoop835
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Hi all,
I have read explanations on pipelined ADC in CMOS Circuit Design, layout and simulation by R.J. Baker. I have attached the block diagram of 3-bit pipelined ADC. My problem is I cannot fully understand the equations stated in the book. I hope someone can explain these equations in a simple n easy-to-understand manner.
*****************************************************************
The 1-bit per stage ADC can be analyzed by examining the switching point of each comparator for the ideal case. From the block diagram attached, assuming all the components are ideal, let Vin1 represents the value of the input voltage when the first comparator switches. This occurs when
Vin1=1/2*vref
The positive input voltage on the second comparator, Vp2 can be written in terms of the previous stage, or
Vp2=(Vin-1/2*Dn-1*Vref)*2
Where Dn-1 is the MSB output from the first comparator and is either 1 or 0. The second comparator switches when Vp2=1/2Vref. The value for Vin at this point, denoted as Vin2, is
Vin2= 1/2*Dn-1*Vref+1/4
Continuing on in a similar manner, we can write the value of the voltage on the positive input of the third comparator in terms of the previous two stages as
Vp3=( (Vin-1/2*Dn-1*Vref)*2 - (1/2*Dn-2*Vref) )*2
and the third comparator switch when Vp3=1/2Vref, which corresponds to the point at which Vin becomes
Vin3=1/2*Dn-1*Vref+1/4*Dn-2*Vref+1/8Vref
By now a general trend can be recognised and the value of Vin can be derived for the point at which the comparator of the Nth stage switches. This expression can be written as
Vin,N =
1/2*Dn-1*Vref+1/4*Dn-2*Vref+1/8*Dn-3*Vref+.......+1/2n-1*D1*Vref+1/2n*Vref
The preceding equation does not include D0. This is because D0 is the output of the Nth stage comparator.
I APPRECIATE ANY INPUT
Thks
I have read explanations on pipelined ADC in CMOS Circuit Design, layout and simulation by R.J. Baker. I have attached the block diagram of 3-bit pipelined ADC. My problem is I cannot fully understand the equations stated in the book. I hope someone can explain these equations in a simple n easy-to-understand manner.
*****************************************************************
The 1-bit per stage ADC can be analyzed by examining the switching point of each comparator for the ideal case. From the block diagram attached, assuming all the components are ideal, let Vin1 represents the value of the input voltage when the first comparator switches. This occurs when
Vin1=1/2*vref
The positive input voltage on the second comparator, Vp2 can be written in terms of the previous stage, or
Vp2=(Vin-1/2*Dn-1*Vref)*2
Where Dn-1 is the MSB output from the first comparator and is either 1 or 0. The second comparator switches when Vp2=1/2Vref. The value for Vin at this point, denoted as Vin2, is
Vin2= 1/2*Dn-1*Vref+1/4
Continuing on in a similar manner, we can write the value of the voltage on the positive input of the third comparator in terms of the previous two stages as
Vp3=( (Vin-1/2*Dn-1*Vref)*2 - (1/2*Dn-2*Vref) )*2
and the third comparator switch when Vp3=1/2Vref, which corresponds to the point at which Vin becomes
Vin3=1/2*Dn-1*Vref+1/4*Dn-2*Vref+1/8Vref
By now a general trend can be recognised and the value of Vin can be derived for the point at which the comparator of the Nth stage switches. This expression can be written as
Vin,N =
1/2*Dn-1*Vref+1/4*Dn-2*Vref+1/8*Dn-3*Vref+.......+1/2n-1*D1*Vref+1/2n*Vref
The preceding equation does not include D0. This is because D0 is the output of the Nth stage comparator.
I APPRECIATE ANY INPUT
Thks