Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Simple DFF in Liberty Library

Status
Not open for further replies.

trav1s

Full Member level 1
Joined
Nov 11, 2010
Messages
98
Helped
29
Reputation
60
Reaction score
28
Trophy points
1,318
Location
Japan
Activity points
2,025
I am trying to synthesize using SOC Encounter, but I am faced with the following error.

Error : Unable to map design without a suitable flip-flop. [MAP-2] [synthesize ]
: Instance 'U_DIV12/clk_count_reg[0]' requires a simple flip-flop.
: Check the libraries for necessary flop cell. The cell could be marked unusable.


I don't understand why it won't accept my library entry for the simple DFF. Here is what I have:

cell(dff) {
area : 1;
pin (CLK) {
direction : input;
capacitance : 1;
}
pin (D) {
nextstate_type : data;
direction : input;
capacitance : 1;
}
/* ff/latch format */
ff (IQ) {
next_state : "D" ;
clocked_on : "CLK" ;
}
/* statetable format */
statetable(" D CLK", "IQ") {
table : " H/L R : - : H/L,\
- ~R : - : N";
}
pin(Q) {
direction : output ;
function:"IQ";
}
}


Can anyone tell me what is wrong with this syntax? Why will Encounter not accept this cell?
 

Yes, that was the problem. For those with similar troubles it has been corrected to the following:


cell(dff_c2mosD) {
area : 32.32;
cell_leakage_power : 5.9;
cell_footprint : "dff_c2mosD"
pin (C) {
direction : input;
capacitance : 5.25;
fanout_load : 4.5;
}
pin (D) {
direction : input;
capacitance : 1.32;
fanout_load : 1;
timing () {
related_pin : "C" ;
timing_type : hold_rising;
intrinsic_rise : -600;
intrinsic_fall : -600;
}
timing () {
related_pin : "C" ;
timing_type : setup_rising ;
intrinsic_rise : 900;
intrinsic_fall : 900;
}
}

ff (IQ, InQ) {
next_state: "D";
clocked_on: "C";
}
pin(Q) {
direction : output ;
max_capacitance : 8.2 ;
max_fanout : 7 ;
function : "IQ";
timing(){
timing_type : rising_edge;
intrinsic_rise: 870;
intrinsic_fall: 1930;
rise_resistance:169;
fall_resistance:93;
related_pin : "C" ;
}
}
pin(nQ) {
direction : output ;
max_capacitance : 5.8 ;
max_fanout : 5 ;
function : "InQ";
timing(){
timing_type : rising_edge;
intrinsic_rise: 1170;
intrinsic_fall: 260;
rise_resistance:585;
fall_resistance:207;
related_pin : "C" ;
}
}
}/* end of dff_c2mosD*/
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top