Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It is not to see only timing voilation there are lot of reason:
1. you need to check allyour interface.
2. there is no stuck at 0/1 in any flop i.e scan chain is proper.
3. you need to check there is no defect in any of the memory by MBIST.
4. Basic functionality of your chip.
5. there are different type of tests for temperature etc.
For silicon validation... there are always.. DFx (Design for *) features added in to the design...
It goes with the RTL on die...Once the silicon is ready, this feature are used to test whether the silicon is healthy or not. Interms of functionality, routing, all paths, etc.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
