tok47
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Hi ALL,
Do anyone familiar with the flow / processes to characterize std cell library at silicon level?
Rdgs
YY
i want to understand the flow....
(1) normally how long it will take.
(2) what are the tests need to be done
Do anyone familiar with the flow / processes to characterize std cell library at silicon level?
Rdgs
YY
--- Updated ---
i want to understand the flow....
(1) normally how long it will take.
(2) what are the tests need to be done
Last edited: