signed addition problems and overflows

[kannan2590]

i have studied and understood signed additions concept when overflow will occur and not.if both numbers are negative and answer is positive then overflow will be there . but when i am imlementing fir filter in vhdl and the overflow occurs while signed addition is there any solution to detect that overflow and i want to get correct output samples without the overflow problem. is there any permanent solution or code in vhdl. so that i can get correct output sample considering the overflow bit . is there any need to write code for overflow detection while addition along with fir filter code in vhdl.

 

[FvM]

i want to get correct output samples without the overflow problem

Strictly spoken, you'll only get correct output samples by providing enough extra bits before adding the numbers. In some situations, result saturation to maximal respectively minimal signed value is wanted, If you use IEEE fixedpoint libraries, you'll get features like saturation without writing your own code.

Working with numeric_std library, a function can easily provide addition with saturation

FUNCTION SUM (X1,X2: SIGNED) RETURN SIGNED IS
VARIABLE S:SIGNED(X1'length-1 downto 0);
  BEGIN
    S:=X1+X2;
    IF X1>=0 AND X2>=0 AND S<0 THEN
      S:= (others => '1');
      S(S'left):='0';
    ELSIF X1<0 AND X2<0 AND S>=0 THEN
      S(S'left-1 downto 0):= (others => '0');
      S(S'left):='1';
    END IF;		
  RETURN S;
END;