Signal oversampling for very low jitter in Spartan FPGA

[Aoxomox]

fpga jitter

Hallo,

I have a question concerning a method to sample a digital signal in a Spartan-3 FPGA with very low jitter. The external signal input to the FPGA is not synchronized to the FPGA clock signal. I want to implement a synchronous counter (retriggerable monoflop) that can be triggered by the rising edge of the sampled signal. The absolute delay between the rising edge of the input signal and the start of my counter is not critical. BUT the jitter of the output signal related to the input signals should be less than 1ns. The maximum sampling frequency is about 250MHz, so a period of 4ns.

My idea is that I could use the DCM (digital clock management) with say 250MHz input clock to generate 4 clock signals with a phase shift of 0, 90, 180 & 270 degrees to the input clock. Thus I will have four rising edges distributed with 1ns phase shift. Then I would implement 4 counters each running on one of the four generated clocks. The enable signal for the counters is my signal to sample.

Does anyone have ideas, comments or maybe an Appnote?

Thanks for your help,

Aoxomox

 

[echo47]

digital counter propagation delay xilinx

That seems like a lot of counters. Are you trying to measure the time that an edge occurred to 1ns resolution? This app note describes 8X oversampling in a Virtex device. Maybe it will give you some ideas, or maybe you can adapt it to Spartan-3.
https://www.xilinx.com/bvdocs/appnotes/xapp861.pdf

I once arranged a long carry chain as a delay line, and latched the taps in a register at 200 MHz. That gave me about 7 gigasamples/sec in a Spartan-3. Here's an app note that seems vaguely similar:
https://www.xilinx.com/bvdocs/appnotes/xapp671.pdf

You may find some other techniques in this collection of app notes:
**broken link removed**

 

[Aoxomox]

spartan3 fpga carry chain delay example

Very good idea echo47,

i can use an asynchronous input delay line as described in the Appnote 671 with only one clock signal. A start signal will trigger my counter and i place a similar asynchronous delay line at the output of my counter to adjust the output delay exactly to the measured input delay. Then the propagation delay will constant in a rangefar better than the required 1ns.

What I need then is to make myself familiar with the timing constraints in WebPack...


Thanks,
Aoxomox