Signal Integrity question...

[mkbs]

Hi to all,
this is the first time for me,to consider SI issues.
What's the correct flow to take in this case ?
I think :
1) Define stackUP with the supplier
2) Define PCB Impedence (but I don't know the right value 50?...70? how I decide it ?)
3) calculate the right width trace for each layer
4) Check signals with likely SI problem and if necessary, add a termination

This flow is correct or not ? At the end I needs always a controlled impedanze pcb
to avoid SI problems,isn't it ?

Many tanks

mkbs

 

[DavidReina]

well, the first step is to know what are you going to design and the general speed buses.
then you should know if you have any manufacturing constraints (such as lead free assembly, HF compliance, overall thickness, etc.) with that in mind you select a material (typically, your first selection is a low cost material) and select the number of layers that are going to be needed to route the signals (less layers, less cost but compromise the routing and power delivery).

once you have selected your material (the vendor may suggest the material that they are more comfortable with) you need to give the vendor two main constraints: impedance and pitch. these values are given by the interfaces that you are routing, you should review the suggested impedance on the application note in the data sheet of each device (typically 50 ohm Single Ended, and 100 ohm Differential), the minimum pitch required is the distance (center to center) of the component pins (use the minimum spacing). with these data, the vendor will give you the geometries of the transmission lines.

then you have to simulate each interface/bus, if you do not meet the required specifications, you play with the physical aspects of the routing, if this does not work you might want to change the material to a lower Dk and Df values (not loosing the manufacturing perspective)

the signals that you want to simulate are the signals electrically short (routing length is 1/10 of wavelength) and the high speed signals

you need to come up with routing rules for the layout designer in oder to avoid SI problems... there are a lot of thumb rules that may help you on the web.

hope this little information helps you
-D