rawbus
Member level 1
I have an ADC that samples 12-bits at 65 MHz that I'm feeding into an FPGA. At the moment, I'm just trying to evaluate the ADC. It has a typical SNR of 71.6 dBFs, a SINAD of 71.5 dBFs, THD of 93dbc. When I put a low frequency sinusoidal signal from a HP 33120A signal generator at around 100kHz I get noise that makes it hard to find the min/max. The signal generator has a harmonic distortion of -45 dBc. There is a lot of toggling back and forth and the max value that the ADC reads in a given cycle doesn't correlate to where the max/min should be, or I get multiple max/min that can be up to 8 cycles apart.
If I put an LC low pass filter on the cable input, lets say DC to 2 MHZ, would that be the solution to my problem of getting rid of the noise or is that the wrong approach?
If I put an LC low pass filter on the cable input, lets say DC to 2 MHZ, would that be the solution to my problem of getting rid of the noise or is that the wrong approach?