Hi,
signal integrity (or SI) refers to PCB interconnection design. Therefore each piece of trace needs to be indicated in the simulation model.
Each piece of trace is a TRANSMISSION LINE (like 50 ohm RF stuff you know) characterized by its characteristic impedance (be careful it is not necessary 50 ohm) and its lenght, that, in this case, Hyperlinx models as its delay.
If you see Fig. 3.2, you have your driver IC, then a first Transmission Line (from now on TL) going to the T-split, and then other two TL going to the 2 74xxxx inputs which are the receivers.
Following the same scheme you should find out the equivalent schematic of Fig. 3.3.
Good Luck