Re: signal from 1.8 to 3.6 ( circuit req ) . But my VDD is
They've already told you what to do. I think the best you can do is split your problem in two. First assume you have ideal 3.6V and do a very preliminary design of the PLL. See if it fits within the rails also for 10% variation of vdd. If it is OK, check a couple of things: The minimum supply it can work with and the current consumption.
Keep in mind that it is very difficult to get the whole 3.6V from a voltage doubler, for instance. You would normally get 3.4V or so depending on the load (current consumption of the PLL)
Depending on the frequency of the clock that you can use for the charge pump, you can estimate the size of the capacitors to be used. The way you do this is: As I told you, the voltage is going to drop from the max possible (i.e. 3.6V). You specify the voltage drop that you want and then the capacitor equals I/(fV)