Binome
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Hi,
what I want is an internal clock that could be configured at the synthesis time between 3 optional frequencies. I have a first original clock (say "clk") and then I want clk/10 or clk/20 or clk/50 to be the internal design clock depending on a user choice.
I use an Altera Cyclone IV FPGA.
What I thought to do was to use a PLL to create the 3 signals, a generic integer and a multiplexer choosing one of the 3 signals depending on the generic to assign it to the component clock.
I was always told not to use logic to drive clock so is the mux eliminated at the synthesis runtime to have only a simple clock signal? Or is there a better way to do it?
what I want is an internal clock that could be configured at the synthesis time between 3 optional frequencies. I have a first original clock (say "clk") and then I want clk/10 or clk/20 or clk/50 to be the internal design clock depending on a user choice.
I use an Altera Cyclone IV FPGA.
What I thought to do was to use a PLL to create the 3 signals, a generic integer and a multiplexer choosing one of the 3 signals depending on the generic to assign it to the component clock.
I was always told not to use logic to drive clock so is the mux eliminated at the synthesis runtime to have only a simple clock signal? Or is there a better way to do it?