signal depending on a generic

[Binome]

Hi,
what I want is an internal clock that could be configured at the synthesis time between 3 optional frequencies. I have a first original clock (say "clk") and then I want clk/10 or clk/20 or clk/50 to be the internal design clock depending on a user choice.
I use an Altera Cyclone IV FPGA.
What I thought to do was to use a PLL to create the 3 signals, a generic integer and a multiplexer choosing one of the 3 signals depending on the generic to assign it to the component clock.
I was always told not to use logic to drive clock so is the mux eliminated at the synthesis runtime to have only a simple clock signal? Or is there a better way to do it?

 

[TrickyDicky]

Why not simply make three clock enable signals if they are all related to the make clk? it is much simpler and easily implemented.

 

[moh.haroun]

you may use a clock multiplexer. refer to this link it might help
https://www.altera.com/en_US/pdfs/literature/ug/ug_altclock.pdf

 

[TrickyDicky]

you may use a clock multiplexer. refer to this link it might help
https://www.altera.com/en_US/pdfs/literature/ug/ug_altclock.pdf

You may - but I would highly reocmmend you dont. clock enables are far easier to control, creating timing for and dont require clocking circuitry. They fit into what the OP wants from his vague description.

 

[FvM]

None of the answers seems to refer to the question "configured at the synthesis time between 3 optional frequencies". A generic won't generate actual logic or a multiplexer. The appropriate solution is to connect the clock inside a generate statement, or use different PLL parameter sets respectively alternative PLL instances.

Using a mux with constant selection will work similar to a generate statement, but cause a few connectivity warnings.

 

[moh.haroun]

Using a mux with constant selection will work similar to a generate statement, but cause a few connectivity warnings.

That what I told him to do.

 

[FvM]

That what I told him to do.

Not exactly. There will be no actual multiplexer or clock control block. The compiler generates a single PLL output and removes the two unused ones depending on the generic. In a directly instantiated PLL, you would only change a divisor value.