signal demotion from global clk to normal, in Actel Libero

[buenos]

global clk

hi

it is a common problem, that the synthesizer or the p&r program assigns normal signals to global clock networks (because of the big fanout on it), and then it does not let me to assign the signal to the pin I wanted, it only lets me to assign it to one of the few global-capable pins. Normally we can override this by specifying that the signal is NOT A GLOBAL. This is the signal demotion.

I know how to do it with Xilinx (top level VHDL, attribute BUFFER_TYPE...), but now I am working with in the actel development software, and I have to do demotion, but I dont know how.
probably I have to write into one of the constraint files, but to which one? and what is the syntax? please tell me an example.

 

[Booleano]

actel toplevel vhdl example

hi,


in the .pdc file try:


unassign_global_clock -net netname


Exceptions
You cannot assign “essential” clock nets to regular nets. Clock nets that are driven by the following macros are “essential” global nets: CLKDLY, PLL, and CLKBIBUF.

Examples
unassign_global_clock -net globalReset


B.

 

[buenos]

actel libero pdc file

hi

thanks. i think there were some problems doing it in the pdc, i dont remember what it was...
but finally i found the solution:
this goes ito the toplevel VHDL file, after the portlist:
attribute syn_noclockbuf:boolean;
attribute syn_noclockbuf of signalname : signal is true;