Signal cannot be synthesized

[nakshathra]

the below code shows up this error when i try to synthesize it.. can sumone please sort out!

ERROR:Xst:827 - "C:/Documents and Settings/Administrator/Desktop/xilinx prgms/tr/tr.vhd" line 64: Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

entity port:-
y as output std_logic_vector(3 downto 0)
em as input std_logic_vector(3 downto 0)
clkout as input
_____________________________________________________________________________________________________________________
architecture signals:-
signal y_temp:std_logic_vector(3 downto 0):= "0000";
type st is (s0,s1,s2,s3,emergency);
signal state:st;
signal temp_out,clkout: std_logic := '0';
______________________________________________________________________________________________________________________

process(clkout,em)
variable count,count_em: integer := 0;
variable temp: std_logic_vector(3 downto 0);
variable pr_st: st;

begin

case state is
when s0 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0001"; count:= count + 1;
else state<= s1; count:= 0; end if;
else null; end if; end if;

when s1 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0010"; count:= count + 1;
else state<= s2; count:= 0; end if; else null; end if; end if;

when s2 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0100"; count:= count + 1;
else state<= s3; count:= 0; end if; else null; end if; end if;

when s3 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "1000"; count:= count + 1;
else state<= s0; count:= 0; end if;else null; end if; end if;

when emergency => if(clkout ='1' and clkout' event) then
if (count_em < 10) then
count_em:=count_em+1;
else
y_temp<=temp;
state<= pr_st;
count:=count + 3;
count_em:=0;
end if; else null ;end if;

end case;

end process;

 

[aruipksni]

the below code shows up this error when i try to synthesize it.. can sumone please sort out!

ERROR:Xst:827 - "C:/Documents and Settings/Administrator/Desktop/xilinx prgms/tr/tr.vhd" line 64: Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

entity port:-
y as output std_logic_vector(3 downto 0)
em as input std_logic_vector(3 downto 0)
clkout as input
_____________________________________________________________________________________________________________________
architecture signals:-
signal y_temp:std_logic_vector(3 downto 0):= "0000";
type st is (s0,s1,s2,s3,emergency);
signal state:st;
signal temp_out,clkout: std_logic := '0';
______________________________________________________________________________________________________________________

process(clkout,em)
variable count,count_em: integer := 0;
variable temp: std_logic_vector(3 downto 0);
variable pr_st: st;

begin

case state is
when s0 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0001"; count:= count + 1;
else state<= s1; count:= 0; end if;
else null; end if; end if;

when s1 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0010"; count:= count + 1;
else state<= s2; count:= 0; end if; else null; end if; end if;

when s2 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "0100"; count:= count + 1;
else state<= s3; count:= 0; end if; else null; end if; end if;

when s3 => if(em /= "0000") then temp:=y_temp; y_temp<=em; pr_st := state; state<= emergency; else
if(clkout ='1' and clkout' event) then
if(count<4) then y_temp<= "1000"; count:= count + 1;
else state<= s0; count:= 0; end if;else null; end if; end if;

when emergency => if(clkout ='1' and clkout' event) then
if (count_em < 10) then
count_em:=count_em+1;
else
y_temp<=temp;
state<= pr_st;
count:=count + 3;
count_em:=0;
end if; else null ;end if;

end case;

end process;

it means you should stick to standard format of sequential process presentation i.e :

[syntax=vhdl]
process (clk, async_rst_n) 

begin
  if (async_rst_n ='0') then
    -- state <= S0;
  elsif rising_edge(clk) then 
    case state is
       when S0 =>
         --PUT CODE HERE
       when S1 =>
         --PUT CODE HERE
       when S2 =>
         --PUT CODE HERE
       when S3 =>
         --PUT CODE HERE
       -- more states ....
    end case;
  end if;
end process;
[/syntax]

 

[FvM]

You are assigning y_temp both inside and outside a clock edge sensitive condition which isn't synthesizable. You can either make y_temp a registered or a combinational signal, but not both simultaneously.

It's also bad style to assign the same signal in multiple clock edge sensitive conditions, although your design compiler might be able to understand it.

Instead you should try with a single "if(clkout ='1' and clkout' event) then" around the case statement.