Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Sigma Delta - Two stage decimation filter

Status
Not open for further replies.

analog_fever

Junior Member level 3
Joined
Dec 26, 2008
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
USA
Activity points
1,519
I am designing a two stage filter to do decimation at the output of a Sigma Delta modulator. Here is the spec -

Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Output resolution - 13 bits.

The filter, and the modulator is reset every 100 clock cycles.

To accomplish this, I used a 5 stage CIC filter to decimate by 20 for the first stage. For the second stage I am hoping to use an LPF to decimate by 5.

1. Any suggestions on a multiplier free LPF implementation?
2. Will a CIC work for the second stage also?
 

hobgoblin

Junior Member level 1
Joined
Feb 1, 2007
Messages
19
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,416
1. Any suggestions on a multiplier free LPF implementation?
Even if you manage to build a multiplierless LPF it is very likely that it won't have good performance.

2. Will a CIC work for the second stage also?
It may or may not depending on bandwidth of the signal of interest. You may end up with a situation when the order of a CIC required to satisfy system characteristics will be too large. Also don't forget about the passband droop of CIC filters. Try to evaluate performance of a cascaded combination of two CIC filters in MATLAB.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top