dawson
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i've done some simulations on sigma delta ADC. but i think my output is not so correct..anyone can help me out attacedh are my design and waveforms
mainly the decimation design im not sure of.
matlab simulink
1st order sigma delta adc
input: 2V Fb=1kHz , OSR=16 times
the 1 bit DAC simply is matlab m function code
function y = DAC_1_bit(u)
if u == 1;
y = 5;
else y = -5;
end
act as a DAC feedback.
i'm not sure about my output bitstream.. should i use the output from D-flipflop - Q (which will be biit stream of 1s and 0s) or from the output function i've create which have a dc valve of +5 for 1s and -5 for 0s latch from the D-flipflop.
output_1_bit code:
function y = Output_1_bit(u)
if u == 1;
y = 5;
else y = -5;
end
after which feed into FIR decimation.. i just try an error with my coefficient no sure what to put in (anyway my input are : FIR filter coefficients :fir1(16,0.015) ,dec factor of 2.
and my output waveform are as follow:
i've notice 2 things:
1) the output has a half cycle at zeros.
2) my signal max and min are not at 2 and -2..
is this acceptable or am i getting it wrong somewhere.
Regards,
Dawson
- - - Updated - - -
Analog simulation
simulation using ltspice with the coefficient calculated based on Richard schreier "understanding delta-sigma data converters"
1st order SDM
and the output bitstream waveform (blue) is
i've notice a things
1)the bit stream when at high +0.8V it should have more 1s, but my waveform seems to be inverted.
after i interface the ltspice waveform to matlab simulink decimation filter.
and the final decimation waveform is indeed inverted and also there a voltage scale up. it should be +0.8 to -0.8V
- - - Updated - - -
what could be the problem
mainly the decimation design im not sure of.
matlab simulink
1st order sigma delta adc
input: 2V Fb=1kHz , OSR=16 times
the 1 bit DAC simply is matlab m function code
function y = DAC_1_bit(u)
if u == 1;
y = 5;
else y = -5;
end
act as a DAC feedback.
i'm not sure about my output bitstream.. should i use the output from D-flipflop - Q (which will be biit stream of 1s and 0s) or from the output function i've create which have a dc valve of +5 for 1s and -5 for 0s latch from the D-flipflop.
output_1_bit code:
function y = Output_1_bit(u)
if u == 1;
y = 5;
else y = -5;
end
after which feed into FIR decimation.. i just try an error with my coefficient no sure what to put in (anyway my input are : FIR filter coefficients :fir1(16,0.015) ,dec factor of 2.
and my output waveform are as follow:
i've notice 2 things:
1) the output has a half cycle at zeros.
2) my signal max and min are not at 2 and -2..
is this acceptable or am i getting it wrong somewhere.
Regards,
Dawson
- - - Updated - - -
Analog simulation
simulation using ltspice with the coefficient calculated based on Richard schreier "understanding delta-sigma data converters"
1st order SDM
and the output bitstream waveform (blue) is
i've notice a things
1)the bit stream when at high +0.8V it should have more 1s, but my waveform seems to be inverted.
after i interface the ltspice waveform to matlab simulink decimation filter.
and the final decimation waveform is indeed inverted and also there a voltage scale up. it should be +0.8 to -0.8V
- - - Updated - - -
what could be the problem
Last edited: