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sigma delta modulator design in verilog-A

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micro designer

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iam working on the verilog-A modeling of first and second order DT sigma delta modulator in synopsys custom designer.
verilog-A code for filter is shown below :

module filter(vin,vout);
input vin;
output vout;
electrical vin, vout;
parameter real n0 = 1.0;
parameter real T = 7.8125e-7 from (0:inf);
parameter real t = 2n from (0:inf);
parameter real d0 = 1.0;
parameter real d1 = -1.0;

analog begin
V(vout) <+ zi_nd (V(vin) , {n0} ,{d0, d1},T );
end



schematic is here schematic.jpeg
first order sdm is working properly as shown in the figureinput-output.png
but when the second order sdm is simulated the output is negative Vmax ie 0.8 V in this case. The filter outputs are going in one direction only as shown here View attachment filter1_out.pdf View attachment filter2_out.pdf instead of filter_out.png in case of first order sdm.

Can anybody help me to understand this problem. Is it required to add saturation blocks after the filter to limit their outputs ?

Thank you
 

radius2

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Your modulator is unstable, the first filter output is going up as high as 50k. You should not put saturation blocks as a stable modulator should
limit the outputs of the filter.

You are already using delaying integrators in your loopfilter i.e 1/(1-z) = z^-1 / (z^-1 - 1) so you don't need an extra delay in your feedback path.
I would guess that this extra delay is causing the instability. Otherwise check the timing carefully.
 

micro designer

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thanks for reply. But the thing is that iam not using delaying integrators it is modeled as 1/(1-(z^-1)) and in first order sdm it is working ok but in second order the modulator is unstable. So please anyone clarify the doubt and suggest solutions.
 

FvM

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I see only positive feedback in the schematic. Why the circuit should be stable?

To be able to compare the coefficients of your circuit with second order SDM from literature, you should use a standard topology with "delaying" integrator, I think.
 

micro designer

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actually the output of the sum block is the difference of the input signals i just named it as a SUM block and even when the delaying integrator is used the output is not correct.
I have implemented the same circuit in MATLAB and it is working fine so what could be the fault in the verilog-A model ?
 

micro designer

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has no one done modeling of sdm in verilog-A ???\
 

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