ali kotb
Member level 3
hello All
I am using veriloga for timing simulations for the sigma delta frac.PLL
I have a problem that the PLL doesn't lock when using sigma delta ,
I was careful when coding the VCO and the multi modulus divider so that I will get the needed frequency band, and the PLL locks fine when its integer PLL
so I guess the problem is with the SDM modelling
answering these Questions can help me in indentifying the solution ?
1) the clk of sigma delta (is it from the ref. osc. or the divider o/p) and why ?
2) for 3rd order mash SDM , the o/p is from -3 to 4. will the change in the SDM o/p stops when the PLL locks , I mean It will continue producing the 8 levels regardless locking, thus the instantaneous VCO frequency will keep on changing.
Regards
I am using veriloga for timing simulations for the sigma delta frac.PLL
I have a problem that the PLL doesn't lock when using sigma delta ,
I was careful when coding the VCO and the multi modulus divider so that I will get the needed frequency band, and the PLL locks fine when its integer PLL
so I guess the problem is with the SDM modelling
answering these Questions can help me in indentifying the solution ?
1) the clk of sigma delta (is it from the ref. osc. or the divider o/p) and why ?
2) for 3rd order mash SDM , the o/p is from -3 to 4. will the change in the SDM o/p stops when the PLL locks , I mean It will continue producing the 8 levels regardless locking, thus the instantaneous VCO frequency will keep on changing.
Regards