SiC MOSFET Dynamic Characteristics_Overshoot

[MBradley]

Hello everyone:
as it always knows the SiC MOSFET turn-off VDS overshoot decrease with the Rg increase, However, as I simulated in Ltspice, when Rg is small to some extent, In other words, when switching speed is fast enough, The overshoot voltage decreased as dvdt_off increasing, anyone who know why? Is the simulation matter?(I tried several cree C3M and E3M model, the phenomineon exists)
Model 1: Cree C3M0040120K

 

[Easy peasy]

are you switching off the exact same current every time - or is the on time longer for the latter curves ?

 

[MBradley]

are you switching off the exact same current every time - or is the on time longer for the latter curves ?

sure the load current is always 40A, below are more waveforms of the simulation

 

[FvM]

I guess parasitics are causing additional gate circuit ringing which has stronger effect on drain waveform at medium gate rise time. Question is if assumed inductance values are realistic.

 

[MBradley]

I guess parasitics are causing additional gate circuit ringing which has stronger effect on drain waveform at medium gate rise time. Question is if assumed inductance values are realistic.

yes it should be some parastic effects, I've removed Lg/Ls/Lss2 and the Phenomenon still exist, maybe this parasitic effect can be used to optimize the switching characteristics if the reason is figure out

 

[kd502]

In simulation you can find what component makes what contribution to overshoot. But for meaningful result you must have accurate representation of parasitics.
Only way to get meaningful result in simulation is to make prototype and fine tune simulation to get similar behaviour. I don't believe in things that has been seen only in simulation.

 

[Easy peasy]

higher Rg isolates the gate drive from the gate proper - hence any tendency to ring is amplified for higher Rg - easy peasy.

 

[24vtingle]

yes and i think we all agree as kd502 said that the junction capacitances are very unlikely to be well modelled by any simulator.
Let alone the inductive parasitics.

You need to get a 100:1 probe on the gate and have a look.
If its high side do with circuit fed by isolation transformer.

 

[MBradley]

In simulation you can find what component makes what contribution to overshoot. But for meaningful result you must have accurate representation of parasitics.
Only way to get meaningful result in simulation is to make prototype and fine tune simulation to get similar behaviour. I don't believe in things that has been seen only in simulation.

thanks, I will do more simulation(Using other model like infineon/onsemi/rohm) to validate if the phenomenon is universal, usually i believe the simulation is 80%-90% euqal to the reality(For power mosfet sipce is almost 100% designed by data fitting), if all model shows same phenomenon, i will do the prototype.

 

[24vtingle]

What you could do in the simulator is take a sic fet...
1...Short its gate to source
2...Apply 400V source from Drain to source
3....Put a 100kHz sine of amplitude say 10V on the 400V...and see what is the AC current into the CDS of the FET...then you will really
see if the sim model correctly models the cds at 400V say.
4...Do it at different voltages to check the cds capacitance at different voltages

 

[kd502]

i believe the simulation is 80%-90% euqal to the reality

Most important parameters can be similar to reality. But ringing always look different than in simulation. Overshoots always look different.
Manufacturers write garbage data to less known parameters of simulation models. We get models are for free, no one cares to give accurate data. PCB parasitics are unknown, and must be measured.
I had done over 2000 spice simulations, that's why I don't believe in anything what I see on screen.

 

[MBradley]

What you could do in the simulator is take a sic fet...
1...Short its gate to source
2...Apply 400V source from Drain to source
3....Put a 100kHz sine of amplitude say 10V on the 400V...and see what is the AC current into the CDS of the FET...then you will really
see if the sim model correctly models the cds at 400V say.
4...Do it at different voltages to check the cds capacitance at different voltages

VERY thanks, I'll try it

Most important parameters can be similar to reality. But ringing always look different than in simulation. Overshoots always look different.
Manufacturers write garbage data to less known parameters of simulation models. We get models are for free, no one cares to give accurate data. PCB parasitics are unknown, and must be measured.
I had done over 2000 spice simulations, that's why I don't believe in anything what I see on screen.

Very thanks, Learned a lot from your explianation