Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There is no specific circuit that will accomplish shutdown.
What you need to do is "AND" your enable/shutdown pin with your start up circuit; and, pull down/up the high impedance nodes to vdd and gnd. If you have simplified ckt, do post it. I am assuming this is a CMOS process
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.