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should i write vip use rvm?

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sansprint

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verilog rvm

hi guys:did you know sth about vip?if i want to write it ,should i based on rvm reference vera?:D
 

Its not necessary to write a VIP with RVM, RVM is a methodology with certain set of libraries as forwarded by synopsis which could be used with VERA. You can always write a VIP in SPECMAN (e) or in that matter any HVL.

A VERA VIP could also be written without following RVM. Now there are quite a number of methodologies provided by many vendors for writing VIP's. Like the CVE, VCE and god knows what all.

There are some efforts being done to make the focal point to a methodology called VMM for SystemVerilog and since SystemVerilog is expected to replace VERA in the Verification spectrum and Verilog 2001 in the Design domain, it makes sense to learn RVM which will in turn be giving way to VMM.
 

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