short violation in soc encounter

[lightcloud]

soc encounter short violation

I have many short violation using soc encounter.
how can I avoid it in flooplan and power plan steps?

 

[leeenghan]

amoebaplace placedesign

Hi,

You should try to understand the cause of the short before attend to resolve it.

In general, try to resolve the congestion after placement (i.e. after placeDesign + optDesign), and not after detailed routing. If you could send a snap shot after placement that show congestion, maybe someone here can give suggestion.

Regards,
Eng Han
www.eda-utilities.com

 

[nmtr]

short violations in soc encounter

now, Soce have a doc with the timing closure. and it gives some good comments about how to do floor-plane and pw-plane when considering the timing closure. you can read it. it may be helpful.

 

[apradeep]

short violation

Hi
did u know th possible cause of shorts
is the design is congested ?
what it placement densiity of the design?
is the shorts are concentrated at some part of the design or else distributed over the design?
is the shorts are for signal or special nets?
if the design has less palcement density, i think the problem would be with floorplan
or else if the design is congested go for placement optimisation
use amoebaplace -congopt -higheffort
please check and correct me if anything is written wrong
Thanks

 

[lightcloud]

Hi,
the short point is all power nets between signal nets. I think maybe signal nets shorted with power
net somewhere.

thanks

 

[conmourtz]

I have the same problem too. Power nets on pads have short violations. Also, some wires from pads that lead to a macro cell on my design have short violations. what could be wrong?