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shiftregister_counter

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seemagoyal44

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can anyone explain what are the connections when counter counts the contents of say 8 bit shift register...means how the both work together...what are the conneections....
 

vamsi_addagada

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hi
module bit_8_ltst_rtst(Q,clk,rst,cntl,D);
output[7:0]Q;
input[7:0]D;
input clk,rst,cntl;
reg[7:0]Q;
always @ (posedge clk or negedge rst)
begin
if(rst)
Q<=1'b0;
else if(cntl)
Q<=D>>5;
else
Q<=D<<5;
end
endmodule
vamsi
 

fail1

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