shift register vhdl
Your way is fail.
In VHDL you don't need to use the loop!
That's the solution:
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift_register is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(7 downto 0);
ldsh : in std_logic; -- load parallel?
en : in std_logic;
w : in std_logic;
q : buffer std_logic_vector(7 downto 0)
);
end shift_register;
architecture shift of shift_register is
signal int_reg :std_logic_vector (7 downto 0);
begin
q <= int_reg;
process (clk,rst)
begin
if rst= '0' then
int_reg <= (others => '0');
elsif (clk'event and clk='1') then
if en='1' then
if ldsh = '1' then
-- d(0)<='0'; -- ???? I've not understood what you wanna do,
-- but this assignment is an error in vhdl,
-- you cannot assign something to an input pin
int_reg <= d; -- parallel load (ok)
else
int_reg(7 downto 1) <= int_reg(6 downto 0);
int_reg(0) <= w;
end if;
end if;
end if;
end process;
end shift;
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The only question is about what you wanna do on ldsh='1' I mean ok it's a parallel load of the register, but what you wanna do when you've written d(0) <= '0'