Shared Variable and Variable (VHDL)?

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Mirzaaur

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shared variable vhdl

hi all,
can anybody please guide me abuout the difference of shared variable in architecture and a normal variable with in proess after synthesis?
I mean shared variable can be accessed from different proessess but variable is local to a process, how they are configured after synthesis?
thanks for your time,

mirzaaur
 

vhdl variable synthesis

If you want to share your variable,
use the generic in the entity....
 

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