Stress=1/((SA+0.5*L)+1/SB+0.5*L))
L refers to the gate length , therefore, only when SA, SB are being bigger, the stress will be smaller.See the fig. below, stress depends on a source area size, MOS tube in the position of the active region and MOS tube size :
the fig. above shows that increase the device to the active area on the edge of the distance can reduce the STI profit effect, so you need to add dummy in need of protection device, and the dummy must be Shared with protected device has a source area, otherwise is invalid.
In addition, due to the biaxial stress increased the hole mobility, reduced the electron mobility, therefore, with the decrease of the gate source voltage and source of PMOS transistor leakage current increase, and NMOS leakage source current is reduced, and the smaller the SA, SB, the more obvious effect.For very small gate voltage, NMOS source of leakage current will increase suddenly, especially in SA, SB when I was a child, this is the result of threshold value changes, the changes in source region is enhanced by stress/suppression system.
maybe the answer will help you.:smile: