Shadow Logic problems - script to XG and DB modes

[dongdong209]

set_testability_configuration

In my module design, there are 2 rams & 1 rom. I want to configure them as black boxes. I use shadow logic DFT. the Design Compiler version has 2 modes:XG & DB mode.
XG mode: set_testability_configuration -type observe -clock_signal....
DB mode: set_wrapper_element ...

who can help me to find specific scripts of the two modes, especially XG mode!

thx!

 

[sunilbudumuru]

set_wrapper_element xg

Hello friend,

for xg mode,

set_testability_configuration -type observe -clock_signal [get_ports [list TEST_CLOCK ]]
set_testability_configuration -type control -clock_signal [get_ports [list TEST_CLOCK ]]

####FOR INPUTS

set_test_point_element -type observe [get_object_name [get_pins A/B/<RAM INPUTDRIVING LOGIC CELL>/Y]] \
-clock_signal TEST_CLOCK\
-power_saving enable

####FOR OUTPUTS
set_test_point_element -type control_01 [get_object_name [get_pins A/B/RAMOUTPUT]] \
-clock_signal TEST_CLOCK

this is the basic script tht u can work on for XG mode. N be careful of any buskeeprs sort of thing at the RAM utputs.

Good luck.

Cheers

Sunil Budumuru
asic-dft.com

 

[dongdong209]

shadow logic in asic

Hello friend,

for xg mode,


####FOR INPUTS

set_test_point_element -type observe [get_object_name [get_pins A/B/<RAM INPUTDRIVING LOGIC CELL>/Y]] \
-clock_signal TEST_CLOCK\
-power_saving enable

####FOR OUTPUTS
set_test_point_element -type control_01 [get_object_name [get_pins A/B/RAMOUTPUT]] \
-clock_signal TEST_CLOCK

When i used the script " [get_object_name [get_pins U3/O]] " , the design compiler points out the u3 is not in the current design NET. I couln't find the reason.(maybe the question is a little foolish. i am a tyro)

thanks！