several questions about on-chip buck converter design( switching mode,including PWM)

[potatosnow]

Hi,all
I am working on a project of on-chip DC-DC buck converter.
I know that the PWM block is used to transfer the error voltage(between Vout and Vref) to be the duty cycle.However I have no idea about how to choose the amplitude Vp of the sawtooth signal in PWM controller. Since the duty cycle d=(Verror/Vp). Can anyone figure out this problem?
My input voltage of the whole circuit is 1.8V, expected to get the output voltage 1.2V, so I prefer to choose the Vref as 1.2V.
Thank you!

 

[checkmate]

For best SNR, you would want it to be as large as possible.
However, you are constrained by things such as error amp output swing, ramp generator headroom requirements, comparator input swing etc.
With a larger ramp, the impact of non-idealities such as error amp and comparator offsets will also be reduced.