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i think it dependes vrey much on the technology (the fab)..
usualy the gate leak is modeled and usualy BSIM3v3 is used.... this is for an IBM fab...
do you have a design manual for you tech?
Not 100% sure but BSIM 3.3 should model gate leakge. Note that in HSPICE it will not show in the OP statement listing - you will have to place 0 voltage source in series with gate voltage to measure it. BTW: in 0.13 gate leakage is not that big but already significant for some applications - like LPF for low jitter PLL.
no bsim 3v3 not model the gate leakage. only bsim4 have model for gate leakage. i think you should consider reading bsim4 manual. you might get something from it. as far as i know, 0.13µ is modeled using bsim3v3. 90nm process and below might use bsim4 since at that process gate leakage may has significant impact to circuit performance.
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