seven segment display

[fakeha_s]

vhdl code for 7 segment display

I want to view my output on seve segment display,do I make a separate verilog file for the code designed for seve segment and use my output here or in the same verilog file (containing my code)i do instantiation

 

[amraldo]

vhdl seven segment display

You should write the HDL file that will derive the 7 segment display.
Regards,
Amr.

 

[fakeha_s]

7 segment display vhdl

I hve a vhdl code tht displas characters as follows how do i use this code to show my 7 bit output named as error_bit
currently the code shows me these values at output but the verilog file i have made its output error_bit i want to display at output not these values(this code has not been designed by me so i am having difficulty t determine where to make changes)would my verilog code be able to work with this vhdl code
0000
1F2E
2E4C
3D6A
4C88
5BA6
6AC4
79E2
8800
972E
A64C
B56A
C488
D3A6
E2C4
F1E2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity my is port (
--swt : in std_logic_vector(3 downto 0);
ssg : out std_logic_vector (6 downto 0);
reset: in std_logic;
clk50: in std_logic;
sel : out std_logic_vector(3 downto 0));
end my;

architecture Behavioral of my is
signal ChangeDigit: std_logic_vector(1 downto 0);
signal count, count1, count2, count3, curr: std_logic_vector ( 3 downto 0);
signal mhertz_count : std_logic_vector(5 downto 0) ; --
signal khertz_count : std_logic_vector(9 downto 0) ; --
signal hertz_count : std_logic_vector(9 downto 0) ; --
signal mhertz_en : std_logic ; --
signal khertz_en : std_logic ; --
signal hertz_en : std_logic ; --

begin
--HEX-to-seven-segment decoder
-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
-- LED: out STD_LOGIC_VECTOR (6 downto 0);
--
-- segment encoding
-- 0
-- ---
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- ---
-- 3
--sel <="1110";
--CE <= '1';
-- with countc Select
-- "6543210"
-- ssg<= "1111001" when "0001", --1
-- "0100100" when "0010", --2
-- "0100100" when "0011", --3
-- "0100100" when "0100", --4
-- "0010010" when "0101", --5
-- "0000010" when "0110", --6
-- "1111000" when "0111", --7
-- "0000000" when "1000", --8
-- "0010000" when "1001", --9
-- "1000000" when others; --0


-- 4-bit synchronous counter with count enable,

process (hertz_en, RESET)
begin
if RESET='1' then
COUNT <= "0000";
elsif hertz_en='1' and hertz_en'event then
COUNT <= COUNT + 1;
end if;
end process;
process (hertz_en, RESET)
begin
if RESET='1' then
COUNT1 <= "0000";
elsif hertz_en='1' and hertz_en'event then
COUNT1 <= COUNT1 - 1;
end if;
end process;
process (hertz_en, RESET)
begin
if RESET='1' then
COUNT2 <= "0000";
elsif hertz_en='1' and hertz_en'event then
COUNT2 <= COUNT2 + 2;
end if;
end process;
process (hertz_en, RESET)
begin
if RESET='1' then
COUNT3 <= "0000";
elsif hertz_en='1' and hertz_en'event then
COUNT3 <= COUNT3 - 2;
end if;
end process;
process (clk50, reset)
begin
if reset = '1' then
mhertz_count <= (others => '0') ;
mhertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
mhertz_count <= mhertz_count + 1 ;
if mhertz_count = "110010" then
mhertz_en <= '1' ;
mhertz_count <= (others => '0') ;
else
mhertz_en <= '0' ;
end if ;
end if ;
end process ;

-- generates a 1 kHz signal from a 1Mhz signal
process (clk50, reset)
begin
if reset = '1' then
khertz_count <= (others => '0') ;
khertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
if mhertz_en = '1' then
khertz_count <= khertz_count + 1 ;
if khertz_count = "1111101000" then
khertz_en <= '1' ;
khertz_count <= (others => '0') ;
else
khertz_en <= '0' ;
end if ;
else
khertz_en <= '0' ;
end if ;
end if ;
end process ;

--generates a 1 Hz signal from a 1 kHz signal
process (clk50, reset)
begin
if reset = '1' then
hertz_count <= (others => '0') ;
hertz_en <= '0' ;
elsif clk50'event and clk50 = '1' then
if khertz_en = '1' then
hertz_count <= hertz_count + 1 ;
if hertz_count = "1111101000" then
hertz_en <= '1' ;
hertz_count <= (others => '0') ;
else
hertz_en <= '0' ;
end if ;
else
hertz_en <= '0' ;
end if ;
end if ;
end process ;

-- This block shows how to multiplex output to different 7-segments
process (clk50, reset)
begin
if reset = '1' then
ssg <= (others => '1') ;
sel <= (others => '1') ;
curr <= (others => '0') ;
elsif clk50'event and clk50 = '1' then
ChangeDigit <= "11" ;
case ChangeDigit is
when "00" => curr <= count ; sel <= "1110" ;
when "01" => curr <= count1; sel <= "1101" ;
when "10" => curr <= count2; sel <= "1011" ;
when others => curr <= count3; sel <= "0111" ;
end case;

if khertz_en = '1' then
ChangeDigit <= ChangeDigit + 1;
else
ChangeDigit <= ChangeDigit;
end if ;
case curr is
when "0000" => ssg <= "1000000" ;
when "0001" => ssg <= "1111001" ;
when "0010" => ssg <= "0100100" ;
when "0011" => ssg <= "0110000" ;
when "0100" => ssg <= "0011001" ;
when "0101" => ssg <= "0010010" ;
when "0110" => ssg <= "0000010" ;
when "0111" => ssg <= "1111000" ;
when "1000" => ssg <= "0000000" ;
when "1001" => ssg <= "0010000" ;
when "1010" => ssg <= "0001000" ;
when "1011" => ssg <= "0000011" ;
when "1100" => ssg <= "1000110" ;
when "1101" => ssg <= "0100001" ;
when "1110" => ssg <= "0000110" ;
when "1111" => ssg <= "0001110" ;
when others => ssg <= "1000000" ;
end case ;

end if ;
end process ;

end Behavioral;

 

[amraldo]

vhdl code for seven segment display

You need first to design a 7-bit binary to 7-segment decoder.
Say u want to output 39 (decimal), u should write a code to encode the 3 & to encode the 9 into the required format to derive the 7-segment dispay. In the sent code there is an example of hex to segment coding, replace it by ur encoding
Then design a controller if needed for the 7 segment display. in this code it is fine no controller is neeeded. It depends upon the FPGA itself.
Connect these blocks to your code & hopefully ISA it will work.

Regards,
Amr.

 

[fakeha_s]

verilog code for 7 segment display

the blocks for ikhz signal ihz signal and multiplexing do not need to be changed is it?
the counter block which i understand is incrementing values being displayed on the segment how do i show my output [6:0]error_detected

multiplexing block is defining if 1 its equivalent hex code
2 its equ code

 

[amraldo]

7 segment display verilog

Yes you should write ur own code to control the output according to ur error code.
Regards,
Amr.

 

[shekar_vlsi]

verilog 7 segment display

most of the FPGA kits are provided with seven segment displays but not decoders,so u have to create a BCD-7SEG decoder to view outputs on 7SEG display. one more thing is all displays on the board will be having single select line.So use them in time multiplexed manner.