Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

setup time and hold time

Status
Not open for further replies.

rajakash

Member level 2
Joined
Nov 9, 2006
Messages
53
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,608
critical to estimate frequency setup hold time

which one is critical to estimate maximum frequency..............
 

setup time is more important deciding maximum frequency .when we decide frequency we r consider set up time
 

mux

thanks friends. .......... do u know in 2:1 mux if select line is 'x' then wat is output.
 

the clock period has be greater than the max critical path time in the circuit
 

you have to be more specific, are you asking what will happen in the simulation or "real" hardware?
Becides theis no X in real hardware...
 

rajakash said:
which one is critical to estimate maximum frequency..............

hold time is 0 for modern FF => setup time is to watch
 

setup time is the limiting factor for max. freq. as for ur second ques. if i/p of mux is 'X' then o/p is also 'x' but if u use casex statement in verilog then this problem will not occur
 

We calculate max. freq by using set up time parameter only.
For hold time we chck only whether our circuit works correctly or not.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top